ess technology, inc. sam0417-051701 1 a ess technology, inc. es3210 video cd processor product brief description the es3210 video cd processor is a highly integrated, high quality and cost-effective single-chip solution for video cd players. based upon esss programmable multimedia processor (pmp) architecture, the es3210 integrates mpeg1 video and audio processing and a full mpeg system stream parser. the es3210 is fully programmable and incorporates a risc-based 32-bit processor as an on- chip video controller (vc) and a supporting 64-bit processor core that functions as an on-chip video processor (vp). the vc module can be used as a microcontroller to provide system and user interface controls, while also being able to support embedded systems applications. the vp module performs mpeg audio and video processing operations such as arbitrary scaling, video standards conversion and video filtering. the mpeg1 system layer bitstream is decoded at up to 9 mb/s at standard intermediate format (sif) resolution with a picture rate of 30 f/s. two channels of mpeg layer 1 or audio layer 2 are decoded simultaneously. the es3210 includes smartscale tm technology for advanced scaling techniques, smartstream tm technology for video error concealment, and smartzoom tm technology for enabling in/out zooming of a particular area of a still picture. additional features include discscan, trackscan, quickscan, on- screen-display (osd), karaoke, playback control (pbc) for video cd 2.0, smart art and entertainment game software. the incoming mpeg1 bit stream from a video cd is passed to the es3210 through its five-wire tdm serial bus, parses the system layer and demultiplexes the video and audio channels. video is decoded and output as yuv or rgb digital pixels to an ntsc or pal video dac/encoder, then to the screen. audio is decoded and passed to the speakers via the audio serial bus, then to an audio dac. the es3210 also has general-purpose auxiliary pins and an integrated audio digital-to-analog converter (dac) interface to reduce the need for external audio glue logic. when coupled with the es3207 video cd companion chip, echo cancellation and vocal reverb are also supported. the echo cancellation feature removes unwanted acoustic reflection from the audio output, while the vocal reverb feature simulates a theater acoustic environment. the es3210 is available in an industry-standard 100-pin thin quad flat pack (tqfp) device package. features ? single-chip video cd processor in a 100-pin tqfp package. ? programmable multimedia processor (pmp) architecture. ? mpeg1 video/audio decoder and system parser. ? video cd 1.1 and 2.0, and audio cd compatible. ? on-chip video interlacing hardware incorporated. ? color space conversion (csc) function supported. ? stc interpretation and video/audio phase-lock loop (pll) ? power management ? 3.3v power supply with 5v tolerant i/os. ? 8- and 16-bit yuv output supported. ? on-chip on screen display (osd) controller supports karaoke lyric and subtitle text display functions. video ? playback control (pbc) for video cd 2.0 supported. ? trick mode functions such as repeat, goto, and set a-b supported. ? smartscale tm for ntsc to pal conversion and vice versa supported. ? smartzoom tm for motion zoom and pan supported. ? smartstream tm for video error concealment supported. ? video fader for fading video image in and out supported. audio ? cd block decoder functions supported. ? 256/384 frame sync audio system clocks supported. ? programmable master clock for external audio dac. ? independent bit clock for audio transmit and receive. ? 3dsound and surround sound supported. software support ? software stack support for the tcp/ip protocols defined by rfc 791 and rfc 793. ? software stack support for the pop3, smtp and snmp internet e-mail protocols defined by rfc 821, rfc 1157and rfc 2449. ? software stack support provided for the http web browsing protocol defined by rfc 1945, rfc 2068 and rfc2616. ? software stack support provided for rtp payload format for mpeg-1/2 and h.261 video streaming protocols defined by character generation and software support for english, big 5/gb chinese and japanese fonts. ? software support for infrared remote control and wireless keyboard.
2 sam0417-051701 ess technology, inc. es3210 product brief es3210 pinout a es3210 pinout figure 1 shows the es3210 device pinout. figure 1 es3210 pinout diagram es3210 pin description table 1 lists the es3210 pin descriptions. 1 vss aux4 aux3 aux2 aux1 aux0 pclk pclk2x cpuclk hsync vsync yuv7 yuv6 yuv5 yuv4 yuv3 yuv2 yuv1 yuv0 vdd vpp la12 la13 la14 la15 la16 la17 aclk aout/sel_pll0 atclk atfs/sel_pll1 doe# ain arclk arfs tdmclk tdmdr tdmfs cas# vss dbus8 dbus7 dbus6 dbus5 dbus4 dbus3 dbus2 dbus1 dbus0 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras# vdd vss reset# dwe# dbus14 dbus15 dbus13 dbus12 dbus11 dbus10 dbus9 ld6 ld7 lwr# loe# lcs3# lcs1# lcs0# la0 la1 la2 la3 la4 la5 la6 la7 la8 la9 la10 la11 vss vdd aux6 aux5 aux7 ld0 ld1 ld2 ld3 ld4 ld5 31 30 51 50 80 81 100 234567891011121314151617181920212223242526272829 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 es3210 100-pin pqfp table 1 es3210 pin description name number i/o definition vdd 1, 31, 51 i voltage supply for 3.3v. ras# 2 o dram row address strobe (active low). dwe# 3 o dram write enable (active low). ma[8:0] 12:4 o dram multiplexed row and column address bus. dbus[15:0] 28:13 i/o dram data bus i/o [15:0]. reset# 29 i system reset (active low). vss 30, 50, 80, 100 i ground. yuv[7:0] 39:32 o yuv[7:0] pixel output data. vsync 40 i/o vertical sync for screen video interface, programmable for rising or falling edge. hsync 41 i/o horizontal sync for screen video interface, programmable for rising or falling edge. cpuclk 42 i risc and system clock input. cpuclk is used only if sel_pll[1:0] = 00. pclk2x 43 i/o pixel clock; two times the actual pixel clock for screen video interface.
ess technology, inc. sam0417-051701 3 es3210 product brief es3210 pin description a pclk 44 i/o pixel clock qualifier in for screen video interface. aux[7:0] 54:52, 49:45 i/o auxiliary control pins (aux0 and aux1 are open collectors). ld[7:0] 62:55 i/o risc interface data bus. lwr# 63 o risc interface write enable (active low). loe# 64 o risc interface output enable (active low). lcs[3,1,0]# 65:67 o risc interface chip select (active low). la[17:0] 87:82, 79:68 o risc interface address bus. vpp 81 i digital supply voltage for 5v. aclk 88 i/o master clock for external audio dac (8.192 mhz, 11.2896 mhz, 12.288 mhz, 16.9344 mhz, and 18.432 mhz). aout/ 89 o dual-purpose pin. aout is the audio interface serial data output sel_pll0 i select pll[0] input. the matrix below lists the available clock frequencies and their respective pll bit settings. atclk 90 i/o audio transmit bit clock. atfs 91 o audio transmit frame sync. sel_pll1 i refer to the description and matrix for sel_pll0 pin 89. doe# 92 o dram output enable (active low). ain 93 i audio serial data input. arclk 94 i audio receive bit clock. arfs 95 i audio receive frame sync. tdmclk 96 i tdm interface serial clock. tdmdr 97 i tdm interface serial data receive. tdmfs 98 i tdm interface frame sync. cas# 99 o dram column address strobe bank 0 (active low). table 1 es3210 pin description (continued) name number i/o definition sel_pll1 sel_pll0 clock output 0 0 bypass pll 0154.0 mhz 1067.5 mhz 1181.0 mhz
4 ? 1997-2001 ess technology, inc. all rights reserved sam0417-051701 es3210 product brief mechanical dimensions a ess technology, inc. 48401 fremont blvd. fremont, ca 94538 tel: 510 - 492-1088 fax: 510 - 492-1098 no part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ess technology, inc. ess technology, inc. makes no representations or warranties regarding the content of this document. all specifications are subject to change without prior notice. ess technology, inc. assumes no responsibility for any errors contained herein. (p) u.s. patent 4,214,125 and others, other patents pending. video drive ? is a registered trademark of ess technology, inc. all other trademarks are owned by their respective holders and are used for identification purposes only. mechanical dimensions figure 2 shows the mechanical dimensions of the es3210 package. figure 2 es3210 mechanical dimensions ordering information part number description package es3210 video cd processor 100-pin pqfp symbol description millimeters min nom max d lead to lead, x-axis 23.65 23.90 24.15 d1 packages outside, x-axis 19.90 20.00 20.10 e lead to lead, y-axis 17.65 17.90 18.15 e1 packages outside, y-axis 13.90 14.00 14.10 a1 board standoff 0.10 0.25 0.36 a2 package thickness 2.57 2.71 2.87 b lead width 0.20 0.30 0.40 e lead pitch - 0.65 - e1 lead gap 0.24 - - l foot length 0.65 0.80 0.95 l1 lead length 1.88 1.95 2.02 - foot angle 0 - 7 - coplanarity - - 0.102 - leads in x-axis - 30 - - leads in y-axis - 20 - - total leads - 100 - - package type - pqfp - e1 a2 a1 l e d1 b d es3210 e 1 e1 l1
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